1. Field of the Invention
This invention relates generally to methods and structures for improving signal transmission in electronic circuits, and more particularly to methods and structures that enable improvements in rise-time performance for differential output signals.
2. Description of the Related Art
In the design and fabrication of electronic circuits, it is well known that capacitive loading, particularly impedance from parasitic capacitance from electrostatic discharge (ESD) protection circuitry, degrades the signal that is being transmitted on conductive traces or leads. As signals are transmitted on conductive leads separated by dielectric materials in a circuit (for example, a circuit fabricated on a multi-layered semiconductor chip), the signals are impeded by parasitic capacitance from the conductive leads. Also, electronic circuits may be subjected to ESD events by simple human handling. As is well known, ESD protection circuitry is designed to direct charge (i.e., current) from an ESD event away from more sensitive circuit elements to a power rail. However, as with any electronic component, ESD protection circuitry has some amount of intrinsic capacitance, which can impede signal transmission.
For signal transmission, it is particularly important, especially at higher frequencies (e.g., >1 GHz), to maintain good signal integrity. Although capacitive loading is a problem in single-ended data transmission, the problem can be exacerbated when driving differential signals. This is particularly true when a mismatch in capacitive loading is present at a pair of complementary output leads. In this situation, the differential output signal can be significantly degraded since each output leas may be subjected to a different amount of capacitive loading, which causes the output lead to have different slew rates and thus introduce mismatch into the switching behavior of the differential signal. However, even if the capacitive loading is matched, the presence of excessive capacitive loading can still substantially degrade differential signal transmission by slowing down its switching behavior, i.e. increases its low to high slew rate and its high to low slew rate.
As well known in the art, any circuit component has some amount of intrinsic, parasitic, capacitance. Therefore, minimizing capacitive loading along a signal path can be difficult since the signal path itself is a source of capacitive loading. Typically, reducing the size of components that are coupled to a signal path minimizes intrinsic capacitive loads. However, the size of certain circuit components cannot be reduced. For example, ESD protection circuits, which must withstand high voltages, and quickly discharge large current spikes, are generally large and must be attached to input and output pads to protect the integrated circuit (IC). Furthermore, although advances in IC manufacturing has led to reduction of device sizes, the size of ESD circuitry has not followed the same reduction because the amount of charge ESD circuitry must withstand has not seen a reduction. Thus, the size of ESD circuitry has remained relatively unchanged, while other circuit components have been reduced. As a result, ESD protection circuitry will generally add a substantial amount of intrinsic capacitive loading at an output, such as an output signal driver. As an example, at high operating frequencies, such as of 1.25 GHz, ESD protection circuitry should not present capacitive loading greater than 0.8 pF, otherwise the signal from an output driver may be degraded.
In order to minimize this potential problem in high frequency devices, circuit designers have typically designed impedance matching devices to null-out load impedance presented by ESD circuitry, pad capacitance, etc., and ultimately, provide matched output load impedance. Matched load impedance provides an environment where signal integrity can be maintained.
FIG. 1 illustrates a typical impedance matching technique 100 that provides independent and separate impedance matching networks 110a and 110b respectively on output leads 108a and 108b of a differential driver 106. As illustrated in FIG. 1, the differential driver 106 receives complementary signals Din and Din_c on leads 104a and 104b from core circuitry 102. The differential driver 106 produces complementary signals Din′ and Din_c′ on output leads 108a and 108b. To protect the differential driver 106 and core circuitry 102 from ESD events, separate ESD protection circuitry, represented by their effective capacitive loads 112a and 112b, are respectively connected to the first and second output leads 108a and 108b. Each component of the differential output signal carried on the differential output leads 108a and 108b is independently and separately matched to compensate for capacitive loading from parasitic capacitance and each of the effective capacitive loads 112a and 112b. Unfortunately, implementing the impedance matching networks 110a and 110b on-chip requires significant silicon area for their integration. Another drawback of implementing impedance matching networks 110a and 110b is the potential for mismatch between matching networks due to process variations in the IC fabrication process. Consequently, because each impedance matching network 110a and 110b is independently matched, mismatch will still happen between the signals output from the output leads 108a and 108b. 
U.S. Pat. Nos. 6,278,339 and 6,249,193 are directed to methods of impedance matching in single-ended drivers by incorporating an adjustable-length transmission line. The transmission line is adjusted in proportion to the magnitude of transients on the driver circuit output. Parallel conductive lines are formed on a printed circuit board, PCB, and shorted by a movable stub from the transmission line.
Another technique for single-ended driver output matching is set forth in U.S. Pat. No. 6,509,755. This patent disclosed a method of detecting an output current from the driver to the load, and scaling the detected current. The scaled current is then subtracted from the input voltage level, thereby providing a dynamic impedance matching technique.
Also, U.S. Pat. No. 6,522,083 proposed a method of tuning the driver output by using an isolation circuit and matching network coupled to the output driver.
These patents provide ways for individual impedance matching in single ended driver outputs and thus fail to address the potential for mismatch between each of the outputs of a pair of differential outputs. Thus, there is a need for methods and structures that provide improved matching for output signals, and particularly those signals that are driven off chip.